즉 입출력 상태를 가지게 된다.
IOC는 마찬가지로 IO 제어와 관련된다.
IOC0(15H)
|
|
BIT=1 |
BIT=0 |
|
0 |
HSI.0 input Enable |
Disable |
|
1 |
TIMER 2 reset each write |
No action |
|
2 |
HSI.1 input Enable |
Disable |
|
3 |
TIMER 2 external reset Enable |
Disable |
|
4 |
HSI.2 input Enable |
Disable |
|
5 |
TIMER 2 reset source HSI.0 |
T2RST |
|
6 |
HSI.3 input Enable |
Disable |
|
7 |
TIMER 2 Clock source HSI.1 |
T2CLK |
IOC1(16H)
|
|
BIT=1 |
BIT=0 |
|
0 |
SELECT PWM |
SELECT P2.5 |
|
1 |
EXTERNAL INTERRUPT ACH7 |
EXTINT |
|
2 |
TIMER1 OVERFLOW INTERRUPT ENABLE |
DISABLE |
|
3 |
TIMER2 OVERFLOW INTERRUPT ENABLE |
DISABLE |
|
4 |
HSO.4 OUTPUT ENABLE |
DISABLE |
|
5 |
SELECT TXD |
SELECT P2.0 |
|
6 |
HSO.5 OUTPUT ENABLE |
DISABLE |
|
7 |
HSI INTERRUPT FIFO FULL |
HOLDING REGISTER LOADED |
IOC2(0BH)
|
|
BIT=1 |
BIT=0 |
|
0 |
Enable fast increment |
Disable fast increment |
|
1 |
Enable downcount feature |
Disable downcount |
|
2 |
PWM 주기 T=512/f (ms) |
T=1024/f (ms) |
|
3 |
||
|
4 |
The A/D conversion time is 91 states times |
158 states times |
|
5 |
Interrupt on 7FFFH/8000H |
Interrupt on 0FFFFH/0000H |
|
6 |
Count down if IOC2.1=1 |
Count up |
|
7 |
Capture Timer2 into T2CAPUTRE on rising edge |
|
IOS1(16H)
|
0 |
Software timer 0 expired |
|
1 |
Software timer 1 expired |
|
2 |
Software timer 2 expired |
|
3 |
Software timer 3 expired |
|
4 |
Timer 2 has overflow |
|
5 |
Timer 1 has overflow |
|
6 |
HSI FIFO full |
|
7 |
HSI holding register data available |
|
note : reading IOS1 clears bits 0-5 | |
IOS2(17H)
|
0 |
HSO.0 |
|
1 |
HSO.1 |
|
2 |
HSO.2 |
|
3 |
HSO.3 |
|
4 |
HSO.4 |
|
5 |
HSO.5 |
|
6 |
T2RESET |
|
7 |
START A/D |
|
note : IOS2 is cleared when read. | |